Simple general purpose digital computer



Dec. 31, 1963 R. J. A MANNA ETAL 3,116,410

SIMPLE GENERAL PURPOSE DIGITAL COMPUTER 9 Sheets-Sheet 1 Filed Nov. 30.1959 ram flamber- Dec. 31, 1963 R. J. L A MANNA ETAL 3,116,410

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SIMPLE: GENERAL PURPOSE DIGITAL COMPUTER 9 Sheets-Sheet 3 Filed Nov. 30,1959 56 /rum l 71k) Dec. 31, 1963 R. J. LA MANNA ETAL 3,116,410

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Dec. 31, 1963 R. J. LA MANNA ETAL 3,116,410

SIMPLE GENERAL PURPOSE DIGITAL COMPUTER Filed NOV. 30, 1959 9Sheets-Sheet 5 De@ 3l 1963 R. J. A MANNA ETAL 3,116,410

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SIMPLE GENERAL PURPOSE DIGITAL COMPUTER PiIed Nov. zo. 1959 9sheets-sheet s 2 /NVENTE 5f w 'n Pie/:ard J'. LaMarma l/erne H- #Vf/sonfforh e v United States Patent Oli ice 3,116,410 Patented Dec. 31, 19633,116,410 SIMPLE GENERAL PURPOSE DIGITAL COMPUTER Richard J. La Manna,Hanover Township, Verne H. Wilson and Vincent T. Pogorzelski, EastOrange, and Mark Pivovonsky, Lyndhurst, NJ., assignors to MonroeCalculating Machine Company, Orange, N J.

Filed Nov. 30, 1959, Ser. No. 856,183 41 Claims. (Cl. 23S-157) Thisinvention relates to general purpose serial cornputer apparatus. Moreparticularly, in an important aspect, the invention relates to a digitalcomputer having at least two synchronized information circulating loops.

In the present invention, the relatively short or minor loop issynchronized to the relatively long or major loop in an epicyclic timingrelation. The computer operating cycle is based upon the recirculationof the minor loop and is divided into two phases. During the first ofthese one of many command codes is extracted from the minor loop. Duringthe second of these phases the extracted command is executed upon aserially presented operand also circulating in the minor loop and, incertain instances, upon a second operand concurrently presented inserial fashion by the major loop.

This computer is characterized by a displacement type of relativeaddressing. In this type of addressing the address of the group ofcommands next to be executed by the minor loop may be a predetermineddistance removed frorn the location in the major loop of the group ofcommands last transferred to the minor loop. Alternatively this addressmay be determined by specifying the amount of the displacement of thisnext group along the circulating major information loop relative to thecurrent position of the minor loop.

Using relative addresses achieves a high eliciency in the use ofequipment by avoiding the waste of providing the equipment necessary forsearching throughout a serial memory for absolute addresses. Thus, inaccordance with an important feature of our invention, addresses areabsent in certain operations involving transfers from the major to theminor loop.

THEORETICAL DESCRIPTION Our invention discloses a computer which isintermediate on the one hand between a Turing type of computer, which byoperating in a bidirectional serial manner on one binary bit at a time,uses a minimum of equipment at the expense of very slow operation, andon the other hand, a large scale stored-program parallel type ofcomputer, which achieves very high speed operation at the expense ofvoluminous and complex equipment. Because of its efciency, our computeris capable of performing calculations involving business and scienticgeneral purpose programs economically at speeds compatible withelectromechanical input and output devices. At the same time computersin accordance with our invention require far less equipment than othergeneral purpose computers. In addition, our invention teaches a computerorganization which permits the stored program corresponding to a givencomputational purpose or format to be injected into the computer by aseparate program loading device which can be shared by many suchcomputers with consequent economy.

A basic principle of our invention is to use a minor circulating memoryloop of reference information in such a Way that the minor loop at anyinstant contains both a group of operating instructions and multipledigit accumulator information. Our invention, in one preferredembodiment, then divides the time of circulation of this minor loop intotwo phases or half cycles during the first of which, designated precesstime, one of the instructi'o`ns of the group is shifted out of thisminor loop into an instruction register. During the second phase,designated execute time, the remembered instruction may be executed. Dueto this automatic precession of the in structions, each instruction of arelatively large group may be executed in sequence without need forfurther transfer of instructions from the major loop until the entiregroup of instructions in the short, or minor loop is exhausted.

In this way of philosophy of opportunity is applied. Thus, while themain memory loop is moving toward the location of an eventually neededpiece of stored information, the short loop is processing other piecesof stored information which lie on the way to the indicated location.The results of this last noted processing are deposited at relativepositions known to the programmer. This may be considered to be anaddressless type of computing which ows from the continuously activetwo-phasc minor loop in accordance with our invention.

A computer in accordance with our invention may be designed to executedirectly as micro-operations such operations as storage to accumulatorand accumulator to storage transfers, subtract, add, various jumps andconditional operations, and the input and output of a single character.A micro-program instruction corresponds to the performance of a singlesuch operation upon every bit of a following word. It a micro-programinstruction is modified during an execute cycle, the modifiedinstruction advantageously may be executed during the remainder of thecycle.

Other macroscopic operations, such as multiplications, input and outputof entire words, binary to decimal and decimal to binary conversions,and other specic operations that may be required for a particularapplication are programmed in terms of the foregoing primarymicroprogram operations.

Toward further minimizing equipment complexity, structures in accordancewith our invention, employ time sharing of components made possible bythe division of the circulation of the short circulating loop into theseparate time phases of precessing and executing.

COMPONENT PARTS The elements of our invention include the two foregoingmemory loops each with a reading station and a writing station. In thelong or general storage loop, the writing station is downstream from thereading station so that information at a given location may be processedand replaced with the result of the processing at the same location.Conversely, in the short loop the reading station is advantageouslydownstream from the writing station. Thus, the information in the shortloop advantageously may be continuously regenerated. These loops arepreferably in the physical form of tracks on the surface of a magneticdrum, but, within the scope of our invention, they may also comprise amagnetic tape, a shift register, or any type of self-regenerating delayline.

These loops circulate information consisting of words each composed of afixed number of binary bits. These equal length words may be either aninstruction word, or a number word.

ORGANIZATION OF INFORMATION In one preferred arrangement in accordancewith our invention, information is stored in a channel having a xednumber of bits. The information stored in such a channel, by way ofexample, is divided in'to a xed number of storage sectors, sayseventy-nine such sectors. Advantageously this number is an odd numberas later appears. The information of such an illustrative sector isfurther divided into groups. Illustratively, each sector contains asingle binary indicating bit, a flag bit, and a word having thirty-twoadditional binary bits. Each word is further subdivided into a pluralityof subgroups which together include the remaining bits assigned to asector. These subgroups may, for example, have informationalsignificance such as the designation of arithmetic operations to beperformed or, simply, the value of a number.

TIMING Clock means are provided to signal bit time and end of word time,and these times are lnade to be simultaneous for both circulating loops.End of word time is chosen to be coincident with the last bit in eachword, and is conveniently designated taz for the above example, where tuis designated ag bit time.

A feature of our invention, as noted above, is the provision of an oddnumber of words or sectors in the general storage memory loop, and aneven number of words (preferably two) in the shortinstructions-accumulator" loop.

The consequence of this provision is that on successive circulations ofthe general storage loop, a given general storage sector will correspondin time alternately to the rst, or instruction word, and then to thesecond, or operand number word, being circulated in the two-wordinstructions-accurnulator loop. It is this feature which allows any wordin the general storage loop to be read into the short working loopeither as an operator (instruction group), or as an operand (number).Thus, when it is desired to obtain a new group of instructions from thegeneral storage loop, a revolution of the general storage loop isselected in which the desired new instruction word will correspond intime to the instruction part of the short loop, whereas when it isdesired to nd a new operand (number word) from general storage, arevolution of the general storage loop is selected in which the desirednumber corresponds in time to the accumulator word in the short loop.

OPERATION OF THE COMPUTER In accordance with our invention, duringnormal precess time, a word is read from the accumulator-instructionsloop and is permitted by suitable gates to flow through a shift registerhaving as many stages as there are bits in an instruction. The output ofthis shift register is then written back into the short, two word loop.

At the end of word time of this precess phase U32), the gate leading tothe shift register is closed and the shifting operation is stoppedthereby stranding the last (highest order) command in the shiftregister. Due to this diversion from simple regeneration (by passingthrough the shift register), and since each shift occupies one bit time,the original instruction word under discussion will be delayed at theend of word time relative to the short loop by the length of oneinstruction. lt may be seen that each time this process occurs to aninstruction word its information content is circulated or processedwithin the word by one command in the direction of higher order.

A single stage binary counter (ip-flop) is provided to count the end ofword time signals and thereby to provide the two logical signal levelsdividing the computer time into precess time and execute time. When thiscounter signals that precess time is completed, the proper gates areoperated to decode the instruction left in the foregoing shift registerand to execute this instruction on each of the bits of the followingnumber word read from the instructions accumulator loop, or from thegeneral storage loop, or both, depending on the command.

For those commands requiring arithmetic processing, a simple binaryadder-subtractor is provided having two inputs, one output, and acarry-borrow memory flip-flop which may be interrogated or reset by thelogic of the system. When this memory flip-flop is not being used forarithmetic purposes, it serves the important function of being anindependent, conditional reference llip-op for decisions; this is incontradistinction to the usual computer practice of using anaccumulatoroverflow as the condition for a decision` Simultaneously withthe execution of the order, the results of logical operation beingperformed may be recorded, bit-by-bit, either back on theinstructions-accumulator loop, or on the general storage loop.

It is to be noted that, in accordance with a feature of our invention,all recording (writing) operations in our invention are of the typewhich automatically erase whatever previously recorded bits may haveexisted on the loop medium. Thus, a previously stored word is replacedwith a new word.

INSTRUCTION WORD STRUCTURE In a preferred embodiment of our invention,instruction signal combinations, i.e. information subgroups fordesignation of operations to be performed, are of four bits length.These four binary bits give rise to sixteen available instructions whichmay, illustratively, be allocated between twelve arithmetic operationsand four displacement addressing operations. These displacementoperations are those in which, for special programming purposes, thenormal application sequence of operating instructions to storedinformation is interrupted and a new set of operating instructionsintroduced.

These instructions are thus executed in sequence under control of theword counter which repetitively alternates between states representingprecess time and execute time, thereby bringing in a new four bitinstruction from the current instruction word on each precession.

One of the above noted sixteen instructions, a skip instruction, isrepresented by a combination of all zeroes. This skip instruction doesnothing except to regenerate the number in the accumulator portion ofthe short loop. The importance of this instruction appears hereafter.

After each instruction is executed, the instruction is cleared from theshift regitser (replaced by binary zeroes) so that the process of ordercode precession is characterized by a discontinuous march of the loworder Hag bit followed by these zeroes automatically injected from theshift register towards the high order end (last in time) of theinstruction word.

A simplifying feature of our invention is the choice of a binary one forthe flag bit in combination with the rst three automatically followingzero bits to comprise the four bit instruction for an automatic fixedlength displacement command, designated jump. After the last orderwritten by the programmer has been executed, a 1G00 signal combinationarticially generated in the ninth precession enters the shift registerand is decoded to effect a xed displacement addressing operation. A newinstruction word is transferred from the general storage without wastingprogram space in the original instruction word for a jump order.Obviously, the programmer must be sure to provide a new instruction wordin general storage at the fixed jump distance from the end of the lastinstruction written.

It will be seen that this device of so choosing the pattern of a commandcode that its topology produces useful results is one illustration of apowerful method taught by our invention, and, as will be subsequentlydisclosed, used to convert one command code into another on the basis ofa decision.

ADDRESSING OPERATIONS The displacement addressing of our invention isaccomplished by what we designate a jump delay instruction. When thisinstruction is included in an instruction word, room must be left toinclude the binary displacement address at the low order end of theinstruction. This binary address number thus replaces one or moretetrads of bits which would otherwise be instructions. On decoding thejump delay, the logical network registers this fact n a mode" flip-flipmemory, and then does nothing for one execute period except toregenerate the information in the short loop. On the following precessperiod, thc normal instruction word precession (through the shiftregister) is changed and instead,

the remainder of the instruction word, which now comprises the binarynumber representing the displacement address, passes through one of thetwo inputs of the subtracting unit. The subtractors output is stored inthe short instructions-accumulator loop. In this way, by properlysetting the other input of the subtractor, the address number suffers adiminution by one unit each time the short loop undergoes oneregenerative circulation, namely, each two word times. Meanwhile, thenumber word in the accumulator is being regenerated intact during theentire jump.

When the address number in the instruction word has been reduced tozero, this fact is signalled by the condition of the borrow flip-flip,and this combination of conditions causes the logical network toterminate the jump with the reading of a new instruction group word fromthe general storage loop into the instruction word interval of the shortloop.

ln this manner, a relative address has been counted down" to permit thecomputer to select from general storage a new set of commands asdirected by the programmer. It will be seen in the followingspecification that during this count down, the flag bit has theadditional and important function of marking the beginning of theaddress number regardless of the composition of the instruction word.

BRANCHING OPERATIONS Branching in our computer may be accomplished by ajump conditional order. In this case, the xed-displacement (jump order)seeking a new series of instructions is made to be conditional on thestate of a condition indicator flip-flop, which can be made to be amemory for the success or failure or overflow of a previous operation.If this condition indicator memory fliptlop is not in the predeterminedstate to cause a jump, the logic is arranged to change the jumpconditional command into a skip which regenerates the accumulator wordin the short loop and proceeds to the next instruction in the currentseries.

It may be seen that a jump conditional order followed by a jump delayorder, in which the delay or relative address is made to be equal to twocirculations of the general storage loop, can be used to set up aniterative test or interrogation routine. The routine will continue untilsome external condition changes the state of the conditional referenceflip-flop, thereby causing a jump and the starting of a new sequence ofinstructions. This interrogation routine is useful for entering inputinformation if the computer must wait until it receives a keyboardsignal, or in providing output information if the computer must alsowait for a feedback signal from the printer signifying that it is nolonger busy and is ready to receive a new print command.

SPECIAL CONSIDERATIONS It is n characteristic of our invention that theepicyclic circulation is continuous, and, therefore, there can be nostop instruction in its commands. This fact makes the starting procedureof the computer an essential part of our invention, rand it will ibeseen that we disclose a novel method of starting up and shutting downthe machine in such a way as to enter and leave the epicycliccirculation state without destroying the stored program. The ag bits inthe general storage track play an important part in this operation andin the loading operation, by providing an index signal to locate theinitial instruction` word.

Another feature of our invention is the leap cornmand which inhibits theword counter action at 132, thereby effectively interchanging preceisstime and execute time, and making the number word in the short loop aninstruction word and vice versa. This order is useful in abridging thetwo circulation epicyclic correspondence period, and in usinginstruction words which have been built up as a number.

The remaining elements of our invention comprise an input register, ano-utput register, a tetrad counter to distribute input `and outputsignals between parallel and serial presentation, a mode flip-Hop todistinguish between arithmetic and displacement type commands, and atleast one delay flip-flop for giving early or anticipated access to theshort circulating loops.

The gating and reset logic of the system is thus arranged to control theinformation flow between the reading and writing heads of the two loops,the shift register, the add-subtract net, and the input and outputregisters in accordance with signals received from the clock means, wordcounter, shift register, conditional reference ipflop, tetrad counter,and mode ip-llop. In addition, the input and output devices are providedwith switches to signal to the logic their availability.

Thus, in accordance with the invention, structures are provided forachieving related principal objects. These objects are to eliminatequiescent time in the utilization of computer elements thus to simplify,to render more economical, and to heighten ithe reliability of computerstructures.

In achieving these objects it is a feature of the present invention thatthere are provided structures having a relatively short circulatinginformation loop which contains an operand which is subjected tocontinuing modification in accordance with a group of instructionssequentially circulating with `the operand in the information loop.

It is an additional feature of structures in accordance with theinvention that instructions are precessed out of a working informationloop into a staticizing register and then executed upon an operandfollowing the same loop.

lt is a further feature of the invention that there are providedstructures having a series of micro-program instructions sequentiallycirculating in a loop with an accumulator number so that eachmicro-program instructions, in turn, is executed upon the accumulatornumber.

A further feature lies in the provision of structure for the relativeaddressing of gro-ups of instructions in `accordance with bothprogrammed and unprogrammed instruction signal combinations.

Another feature of the invention lies in a circulating information loopin `which an operand may be placed for being subjected to continuingmodification in accordance with a group of instructions sequentiallycirculating with the operand in the information loop.

An additional feature is the provision of structures in whichinstructions `are alternately processed out of a working informationloop into a register and then executed on an operand following in thesame loop.

A still further feature of the invention is the provision of structuresfor accomplishing fixed displacement addressing in response topredetermined instruction signal combinations which selectively initiatetransfers of information from a relatively long loop after apredetermined number of cycles of a relatively short loop.

An additional feature is the provision of logical branching paths uponthe displacement of a relative address which is partially conditioned onthe state of a memory device.

Another feature of the invention is a momo-ry arrangement in which aspecific word location in a major loop corresponds in time to la givenword location in a mino-r loop only on `alternate circulations of themajor loop.

These and other objects, features, and advantages of the invention, bothas to its organization and method of operation, will be betterunderstood by consideration of the appended claims and from `thefollowing description considered in connection with the accompanyingdrawings in which several embodiments of the invention are illustratedyby way of example. It is expressly to be un` derstood, however, thatthe drawings are for the purpose of illustration and description only,and are not intended as a denition of the limits of the invention.

FIGURE l is a generalized illustration, partially in block tandpartially in isometric view of a preferred oomputer according to thepresent invention;

FIGURE 2 is a representation of a portion of the memory channels of thecomputer of FIGURE 1, showing the time correlation between cells of thetiming channel and the corresponding cells of the A-I register;

FIGURE 3, consisting of FIGURES 3a and 3l, is a series of idealizedinformation ow diagrams, each corresponding to a different micro-programoperation;

FIGURE 4, consisting of FIGURES 4a and 4b, is a timing diagramillustrating the operation of an input and output counter;

FIGURE 5, consisting of FIGURES 5a through 5d, is a more detaileddiagram of the reading and writing circuits and the relay circuits ofthe computer of FIGURE l;

FIGURE 6, consisting of FIGURES 6a through 6p, is a series of blockdiagrams showing in detail the various gating networks included withinthe logical network of FIGURE 1;

FIGURE 7, consisting of FIGURES 7a and 7b, is a pair of flow diagrams ofa calculator program written for the computer of FIGURE l; and

FIGURE 8 is a block diagram illustrating information ow in anillustrative structure in accordance with the invention.

Turning now to the gures, FIGURE 1 is a diagram of a computer accordingto the present invention. In a pre ferred embodiment of the presentinvention, a magnetic drum 20 driven by a motor 2.1 has a magnetizablesurface which is divided into four drum channels. A timing or clockchannel 22 is recorded, containing 79 evenly spaced binary word sectors,each having 33 cells. Each cell of u channel is capable of storing asingle bit of information represented by a predetermined state ofmagnetization within the cell. Each of the 79 sectors of the timingchannel 22 corresponds to storages for 33 binary bits.

Within each sector of the timing channel, 32 cells contain binaryrepresenting bits to mark the rst 32 bits of each word and the last cellof each word stores a binary 1" representing spot to identify uniquelythe last bit of each word, which is designated x32. The individualmagnetic spots within the timing channel 22 are detected by a T, timingread head 24 `which generates electrical signals and applies them to atiming pulse generating unit 26, which is described in greater detail inconnection with FIGURE a below.

A second track on the drum 20 is used to create a two word recirculatingmemory loop which is designated the Accumulatonlnstruction channel 28.The Accumulator- Instruction or A-I channel 28 is used to store a rstbinary word representing a number, and a second binary word representinga series of instructions corresponding to operations to be performedupon the number. As will be pointed out in greater detail below, thecirculating two word memory loop or register, mechanized by the A-Ichannel 28, uses only 64 storage cells on the drum corresponding to 64cells of the timing channel 22. The additional two storage cellsnecessary to store two 33-bit groups are provided by two static storageelements, more fully described below. Associated with the A-I channel 28is a writing transducer, the A-lw write head 39 and, separated from itin the direction of drum rotation by a distance equivalent to 64 cellsis a read transducer, the A-Ir read head 32.

The remaining two magnetic channels of the drum are used as informationstorage channels and are designated general storage 1 or GS1 34 andgeneral storage 2 or G82 36. As noted heretofore, general storagechannels each contain 79 binary sectors each of which contains a singleag bit though in other embodiments of the invention a different numberof Hag bits may be advantageous. Within each sector, bits other thaniiag bits make up a word which is further divided into subgroups. Thesubgroups may have an instruction significance or a number significance.In conventional partance they are instruction words or number words. Forclarity of discussion, however, these are considered as "subgroups ofthe larger "vt/ord. Each of the general storage channels 34, 36 has anassociated read transducer, a G51r read head 38 and a G52r read head4i), respectively. Information is entered into the general storagechannels by means of a pair of write transducers, a GSIw write head 42and a G82W write head 44, respectively.

The writing heads of the general storage channels are displaced from thereading heads in the direction of drum rotation by a distance equivalentto six word sectors plus one ccll or 199 cells of the timing channel 22.This arrangement permits information from the general storage channelsto be read from a given sector, operated upon in the A-I register andreturned into general storage, in the same sector replacing the formerinformation by processed information. It is therefore a relativelysimple matter to update" stored quantities. The extra cell between theread and write heads is necessitated by the fact that the generalstorage channel operating circuits include a reading staticizer whichintroduces a one-bit delay that must be accounted for.

As will be explained in more detail below, conveniently the words ingeneral storage have, as a low order or least significant bit, a binaryl representing signal which is designated a at bit. More specically, inthis embodiment, cach sector of the general storage, except for one, hasthis binary "1 ag bit. However, in a predetermined word of one of thegeneral storage channels, the least significant or flag bit position isoccupied by a binary 0. It is this 0 flag bit that serves as an indexpulse to synchronize the circulating loops of the computer, and controlthe START and FILL operations.

A logical gating network 50 is shown only in block form in FIGURE l butis explained in greater detail in connection with FIGURE 6, consistingof FIGURES 6a through 6p, described below. The logical network 50includes the read and write amplifiers and staticizers necessary foroperation of the drum and its associated read and write transducers.Also included within the block, are all of the and and or gates,amplifiers, and inverters, which are necessary to execute the variouslogical functions during the operation of the computer'. These gatecircuits receive signals from the drum transducers during certain timeintervals, operate upon them, and provide signals to the drumtransducers representing the result of a predetermined operation uponconcurrently presented information signals. The predetermined operationscorrespond to the micro-program instructions presented by the A-Ichannels in a prior word time.

Shown, arrayed about the logical gating network 50, is a plurality offlip-flops, indicated by a plurality of individual rectangles. Eachrectangle contains an alphanumeric identifying designation as well as areference character. Each flip-fiop may be a conventional bistablemulti-vibrator, well known in the art, having two inputs and two outputscorresponding respectively to each of the stable states of the Hip-Hop.Each ilipflop receives control signals upon conductors from the logicalgating network 50 for placing the flip-flop in either a set or lrepresenting state or a zero or 0" representing state, and which aredesignated respectively, by the alpha-numeric designation of theflip-flop preceded by the letter S for set and Z for zero. The setoutput conductor has the alpha-numeric designation of the flip-flop andthe zero output conductor has the alpha-numeric designation primed.

An L2 flip-flop 52 is connected to the logic network and is normallyused as a read staticizer for information coming from the A-Ir read head32. An F2 ip-tlop 54 and an F3 flip-flop 56 are connected to the logicalgating network 50 to be used, at different times, as staticizers for theinformation read from the general storage read heads and, during certainoperations further described below, the F3 flip-flop 56 is connected inshift register fashion to receive the output of the L2 Hip-Hop 52. Fourip-ilops, F4 58, F5 60, F6 62, F7 64, are, during certain operations,connected together during the precess period as a four-bit shiftingregister and, as such, staticize four-bit instructions to controloperation upon the succeeding accumulator number.

An F1 Hip-Hop 66 is used primarily as a carry-borrow Hip-flop inarithmetic operations. In other operations of a conditional nature, andin input and output operations, as will be described below, the F1ilip-op 66 serves as a supplementary memory'. Another Hip-hop, the FSflipilop 68, may be considered a two-counter which assumes alternatestable states in successive word intervals. The F8 flip-flop 68 cantherefore be used as a basic reference, the state of which marks theprecess and execute periods, and therefore identifies the signalsappearing at the A-Ir read head 32 of the A-I register as number signalsor instruction signals. In one state, F8, the signals appearing are bitsof an instruction word while in the other F8 state, the signalsrepresenting bits of number words are presented.

An F9 ilip-op 70 is another two-counter that remembers which of the twogeneral storage tracks is in communication with the computer. Each timea track change is instructed, the state of the F9 ip-fiop is changed.The output of the F9 flip-Hop therefore can be used as a logical inputfor head switching as between the general storage tracks, F9" selectingGS1 and F9 selecting GSZ.

A [p32 flip-op 72 is provided to identify uniquely the time intervalcorresponding to the last bit time of each word. The tp32 flip-flop 72is in a rst stable state, w32', during the first 32 bits of each word,but during the last or 33rd bit, designated 132, the hip-flop assumesits other stable state, tp32. The tpgz flip-flop 72 can also be used toidentify the lowest order or ag bit at time tu lof the next succeedingword. Inasmuch as the recirculation path of the A-I register normallyincludes both the L2 flip-op 52 and the F3 ip-fiop 56 to total 66 bitsof storage, when the bit corresponding to tu is staticized in the F3flip-flop 56, and the :p32 llip-ilop 72 is in its tpm representingstable state, the L2 flip-flop 52 will be staticizing the t or flag bitof the next word.

An input-output unit 80 is provided to enable the computer tocommunicate with the external world. A plurality of input keys (notshown) are provided to generate a combination of binary signals on tiveinput conductors and a sixth control signal on a separate conductor. Thelogical gating network 50 applies a seventh signal to the input deviceson a seventh control signal conductor. The gating network 50 provides acombination of signals to the output device on iive output conductorsand a sixth control signal on a separate conductor. The output devicereturns a control signal on a seventh conductor. A multi-conductor inputcable 82 transmits the signals between an input portion 84 of theinput-output unit 80 and the gating network S0. A multi-conductor outputcable 86 transmits signals between the gating network 50 and an outputportion l88 of the input-output unit 80.

A pair of relays R1 90 and R2 92 are provided to facilitate the startingand stopping of the computer. The manner of interconnecting the relaysis shown in greater detail in connection with FIGURE d below. Logicprovided within the logical gating network 50 is responsive to signalsfrom the relays to control the energization and de-energization of theelectromechanical and electronic components associated with thecomputer.

There is shown in FIGURE 2, an instruction subgroup of digits 102, atthe read point of the AI register and a number subgroup 104 in one ofthe general storage channels aligned with a portion 106 of the timingchannel 22 corresponding to one sector. In the preferred embodiment ofthe invention, as was pointed out above, each sector is 33 bits inlength having a flag bit in the lowest order or to position and, in thecase of number 10 words, 32 binary digits. An instruction word containsa flag bit and up to eight, four-bit instructions. In the case ofcertain relative address operations, however, an instruction word hasless than eight instructions, with the remaining group of digitsrepresenting a binary number corresponding to a relative address.

As shown, the cells of the individual channels are arranged in verticalalignment representing concurrence in time only. As is well known tothose familiar with the art, the individual cells in a given channel mayhave any physical position with respect to the cell-s of a differentchannel so long as the read and write transducers are positioned topresent signals synchronized in time. Furthermore, the read transducersare indicated as windows on their respective channels and, in theportion of the A-I channel, the two read staticizers, the L2 and F3flip-flops are also shown as windows on the channel.

It is therefore apparent from FIGURE 2, that the ilag bit signal of thegeneral storage channel words are available at the general storage readtransducers simultaneously with the availability of A-I channel wordflag bit signals at the L2 flip-Hop. This correspondence in time permitsthe output of the F2 ilip-op, when used as the general storage readstaticizer, to be combined with the output of the F3 flip-flop beingused as an A-I read staticizer stage.

As was discussed earlier, the operation of the computer is divided intotwo basic periods corresponding to the half cycles of the A-Icirculating register. `Each half cycle is one word time in length,alternate half cycles being designated precess and execute word times.During each precess word time, four bits of an instruction word,representing a single instruction which corresponds to an operation tobe subsequently performed, are extracted from the instruction word andare staticized in a four-bit register. During the succeeding executeWord time, the staticized bits control the disposition of the numberpresented by the A-I register. In the execute half cycle, the A-Iregister may be considered as an accumulator register, storing a numberto be operated upon. In order to set up each instruction in the four-bitstaticizer, four zeroes are inserted in the A-I register to precess theremaining instructions toward the most significant end of theinstruction word. After eight complete cycles of the A-I register, aninstruction word consists only of the ag bit in the most significant bitposition followed by 32 zeroes.

With instruction signal combinations of four bits each, 16 differentprogram instructions are available to the computer. The selectedmicro-program instructions of the preferred embodiment are set forth inTable 1 below. Table l has been arranged to list each instruction byname, an abbreviation, a binary code number and the declmal numberequivalent of the binary code.

Table 1 Name Abbre- Binary Decimal viation Codo Number Skip SK 0000 0Transfer to General Storage TS 0001 1 Transfer to Accumulator TA 0010 2Extract or Leap: F1=Extract, Fl'= Leap E/L 0011 3 OUT 0100 4 p 1N 0101 5Subtract` (.rcnernl Sto fc Numberfroin Accumulator Number SUB 0110 G AddGeneral Storage Number t0 Aecum ualtor Number ADD 0111 7 Jump 1000 8Change Track Delay 1001 9 Jump Conditional 1010 10 1011 11 1100 12 110113 lll() 14 Leit Shift. (Multiply by 2 llll 15 As seen in FIGURE 2, aninstruction word is arranged with the `most significant bit of the firstinstruction located in the last or t32 bit position. It is understoodthat the flow of information is such that the recorded information movesto the right, passing under a stationary read transducer A-Ir indicatedby the properly designated Window at the right side of the drawing. Inthe instruction word 102, the first instruction to be executed includesfour bits, in, i12, im and 14, stored respectively in the t32, x31, t3()and f2s bit positions. Similarly, the bits of the second instruction,i2, through i2., are stored in cells corresponding to t28 through 125.The bits of the last instruction, 1'81 through i8', are located in thecells t., through t1.

If an instruction word includes a delay type instruction which re-quiresa jump to some relatively remote location in general storage, theinstruction requiring this transfer is followed by a binary number whichrepresents a relative address of the word being sought. This binarynumber is located at the least significant end of the instruction wordand occupies as many cells as are necessary to specify the relativeaddress.

A typical number word 104 contains a flag bit at the low order end `anda plurality of binary digits which may form the number. The mostsignificant digit position, t32, of the number word may be interpretedas a sign bit at the programmers discretion.

Eleven of the sixteen primary operations, set out in Table 1 above, maybe considered arithmetic instructions in that they utilize theaccumulator. These eleven consist o-f the following: transfer to generalstorage (TS), transfer to accumulator (TA), extract-leap (E/L), output(OUT), input (IN), subtract (SUB), add (ADD), clear (CL), right shift(RS), add conditional (ADDc), and left shift (LS). Note that thetransfer to general stor- :age command is the only instruction whichrecords new information in general storage. Also, live of theseinstructions, namely, transfer to accumulator, extract, subtract, add,and add conditional, utilize the general storage read head as the sourceof the second operand.

Four of the sixteen primary commands serve as displacement addressinginstructions. These are the jump group, namely, jump (I), change track(CT), jump conditional (Jc), and jump delay (Irl). These instructionsoperate on the instruction portion of the A-I channel during precesstime in contradistinction to the foregoing arithmetic commands whichoperate on the accumulator portion of the A-I channel during executetime.

The remaining one of the sixteen primary operations is the skipinstruction (SK), so titled because it leaves everything unchanged.

The most effective approach to the description of our invention lies inthe detailed examination of the role played by the nine basic systemflip-flops (F1 to F9) and the two retiming flip-flops, 1.2 and 11232, ineffecting the sixteen primary operations.

In the following discussion, FIGURES 3a-3k are especially useful incorrelating the time sharing functions played by these flip-flops duringeach instruction, and in following the information flow paths for theseoperations.

The F1 Hip-flop 66 is the general purpose conditional memory which isused during the relevant arithmetic operations as the carry-borrowflip-flop for the addersubtractor unit. 1n general, F1 remains staticduring precess word times (except during the jump delay and change trackcommands) so that in effect it carries information forth from a previousexecute word time to a subsequent one.

Thus all the conditional operations (add conditional, jump conditional,extract-leap, jump delay, and change track) are conditioned on theinformation content of F1, remembered from the previous operation. Itshould be noted that the conditional part of the add conditional,extract-leap, and jump conditional commands is whether or not they areto be executed, whereas in the jump delay and the change track commands,the condition of the Fl flip-flop is not a condition to the execution,but instead modulates how much displacement will take place asdetermined by the delay address numbers in the given instruction word.For programming convenience, F1 is usually referred to as the carryflip-flop (designated K flip-flop) although it actually serves as amulti-function conditional register.

During execute word times, tiip-tlop F2 54, serves as the generalstorage read flip-flop in those operations where a general storageoperand is needed. During the input and output instructions, F2 teams upwith the F3 liip-liop S6 to serve as a tetrad counter to identify timeintervals to to t3. In other operations, F2 serves as a counter Hipflopto designate I@ intervals during execute word times. In the precess wordtimes, however, F2 plays an entirely different role. Here it serves as amode flip-flop to designate whether the computer is undergoing a normalprecess word time or if one of the four jump commands (jump, jumpconditional, jump delay, or change track) is being performed. Note thatthe F3 rather than the F2 ip-op serves as the general storage readtiip-iiop when a new instruction word is being transferred from generalstorage to the instruction portion of the A-I channel during a jump typeoperation. Thus it is seen that F2 represents the general storage readflip-flop for number words (during execute word times), whereas forinstruction words (during precess word times) F3 represents the generalstorage flip-flop, when necessary.

During normal precess word times, F3 represents a second A-l channelread flip-flop, in series with the L2 flip-flop. F3 serves this samerole during execute word times for most of the commands. During inputand output, F3 in conjunction with F2 serves as a tetrad counter (fromto to r3) as previously mentioned, but in general F3 represents an A-lchannel read flip-flop whenever it is necessary to use the accumulatoras an operand, regenerate the accumulator, or normally precess theinstructions.

The F4 to F7 flip-flops, 58, 60, 62, 64, represent the four flip-flopsin the command shift register, under control of the F8 tiip-tiop 68. F8may be considered as the Word time counter, in that its sole function inthe computer is to count sector pulses at t32. As such, it serves as afundamental reference flip-flop.

During F8 (precess word time) the command shift register advances theinstruction Word from the A-I channel read head into the A-I write head,as is best noted in FIGURE 3b. The high order tetrad of the instructionword remains locked in the command shift register as F8 ends and F8'(execute word time) begins. During F8' this tetrad is decoded from thecommand shift register as one of the sixteen primary mirco-programinstructions.

During the precession in F8, all the tetrads in the A-I channel areprecessed up one tetrad towards the high order end. Thus the secondhighest order tetrad before the precession now becomes the new highorder tetrad in the instruction word portion of the A-I channel. Assuch, it is in position to be precessed into the command shift registerduring the next F8 precession, where it will be used as the nextoperation code. It follows that the command shift register normallynever advances during F8 since the operation code is being decoded fromit. Conversely, the command shift register always advances during anormal F8 precession (a precession other than one involving a jump typeinstruction) in order to set up the next primary operation code.

The F9 flip-flop 70 represents the change track flipfiop, and socontrols which of the two general storage tracks is selected for readingor writing. This control function is best seen in connection withFIGURES 5a and 5b, described below. The only time that F9 changes isduring a change track instruction (CT). The change track instruction isidentical in all respects to the jump delay instruction, except that theF9 {lip-Hop is triggered to its complementary or opposite state as theinstructions name implies. Thus the change track command is really amember of the jump type (displacement address) instructions identical inall ways to the jump delay except for its one special duty. F9 servesone additional purpose of serving as a fth channel of output to thetypewriter or printer thereby giving the programmer a choice of 32output characters rather than the 16 provided by the four binary digits.

The logical gating diagrams, FIGURES 6er-6p, comprise a detailedschematic of the logical gating network 50 from which those skilled inthe art can reproduce an operating model of our invention.

In the following descriptions of the logical operations of our computerfor each of the sixteen instructions, reference is made to Table l whichsets forth each of them. Particular note `should be made in each case ofthe disposition of the:

(l) The K (F1) flip-Hop (2) General storage word (3) The number word inthe accumulator (l1-132) (4) The low order or flag bit of theaccumulator, to

SKIP (SK) (0000) K, general storage, and the number in the accumulatorremain unchanged. The low order bit of the accumulator is reset to zero.

Translating the foregoing definition into computer logic terminology, itis observed that all that is necessary to achieve this command is toregenerate the number in the accumulator. F1 (the K flip-Hop) andgeneral storage will automatically remain unchanged unless wespecifically write some logic (i.e. provide gates) to change them. TheHow path for this operation is set out in FIGURES 3a' and 5c, and thespecific gate path is shown in FIGURES 6er-6p.

The regeneration of the accumulator requires the information word topass from the A-Ir head, 32, back to the A-IW head 30. Filling in the`gates for this path from FIGURES 6a-6p, signals pass from the A-Ir head312- LS-SLZ [FIGURE 611], G8-G12-G17-F30-SF3 [FIG- URE 6bl, G53-G63-L1[FIGURE 6n], G20-L7 [FIG- URE 6d], to A-Iw head 30.

To illustrate a detailed tracing of such a logical gating path, it maybe seen that, starting in FIGURE 5b the A-Ir head 32 leads through anon-inverting amplifier 110 to generate a signal on conductor L8 andthrough the inverting amplifier 112 to generate a signal on conductorL8'. Thus if a l is read by A-Ir head 32, a relatively high or lrepresenting signal will appear at clock time C1 on lead L8 While if a 0is read by head 32 a relatively high or 1" representing signal willappear within bit time C1 on lead LS'. Turning now to FIGURE 6h, theseleads are shown applied to control the setting of the L2 flipliop, 52.It is to be understood, at this point, that all setting and zeroinginputs to the Hip-flops are clocked by timing pulses C1 which are notnecessarily shown in the figures. The state of output conductors L2 andL2' is then high or not depending on the presence of a l or a 0respectively at the A-Ir head 32 `during the previous bit time. Gates G8and G12 are found in FIGURE 6b, and it may be seen that the foregoing L2signal, together with a signal from gate G8, and the F8' (execute time)signal are all necessary to pass through the and gate G12 to reach orgate G17. The signal path then oontinues through the network designatedF30 to control the setting of the F3 tiip-op 56 one bit time later,thereby generating either F3 or F3'. Gate G55 in FIGURE 611 is dependenton gate G53 and on the foregoing F3 signal, together with A10, tocontinue through gate G63, inverting amplifier 114 to L1'. The signal Lis applied in FIG- URE 6d to gate G20, the output of which generates asignal L7 by a rst inverter 116 and signal L7' by a second inverter 118.Returning to FIGURE 5b, the path leads to the A--lW head 30 via gateG1121, one shot pulse generator 120 and non-inverting amplifier 122 inthe case of an L7 or 1" representing signal to be recorded or via gateG122, one shot 124, and non-inverter 126 in the case of an L7 or 0representing signal.

The F5 diode in G8 and the F6' diode in G53 allow this path to operate.It should be noted that the GS- G12-Gl7 part of this path does notregenerate the low order flag bit (tu) of the accumulator. The reasonfor this is that the F30 net (FIGURE 6b) is timed one bit early becauseof its position in the A-I register circulation loop (this bitrepresents the `unit delay in the F3 ipflop). The F3 llip-op containsthe most significant bit of the instruction tetra-d, which is a 0" atx32 of the previous F8. The low yorder bit of the accumulator number isin L2 :and the F30 net. At 32 of F8, no gate of FIG- URE 6b can transferthe contents of L2 to F3. The F3 flip-flop therefore copies its contentsinto the writing circuits, thereby resetting the IOW order bit positionto 0, thus preventing the regeneration of the low order accumulator bit.

TRANSFER TO GENERAL STORAGE (TS) (0001) (1) The K flip-flop and thenumber in the accumulator remain unchanged. The flag or low order bit ofthe accumulator is reset to i). T'he number in the accumulator istransferred to general storage thereby replacing the number previouslystored there as is shown in the ow path of FIGURE 3C.

Aside from the additional function of transferring the number in theaccumulator to general storage, this command is identical to the skipcommand. Thus the previous description of the skip command servesequally well with respect to K, the regeneration of the accumulator, andthe `loss of the low order accumulator bit. The accumulator regenerationpath given for `the skip command is identical for the transfer togeneral storage command. The path from the A-Ir read head 32 toZF3-G18-L10'- (G114 or C117) and A-Ir read head 32 to SF3-Gi19-L11-(G114 or G117) represent the flow of information signals beingtransferred from the accumulator to the general storage write circuits.The rst of the two paths represents that taken by the Os in theinformation word, `while the second represents the path of the ls.

In the transfer to storage command, it is to be noted that this is theonly one of the primary commands which records into (changes) generalstorage, and that the general storage write heads, GS1w and GSZW, `42,44 are six word times (plus 1 bit) behind the GS1r and GS2r read heads(38, 40) so that the `word replaced by this command is six sectorsremoved from the word concurrently presented by the general storage readheads, G51r and G52, 38, 40.

In decoding the logic for G18 and G19 in the path from the accumulatorto the general storage write circuits, we nd the equivalent of an F2diode ron each of these gates. The F2 flip-flop 54 is set to representtime intervals tlm or to' in the transfer to general storage command.Thus we see that the purpose of these F2 diodes is to protect the flagbit in general storage by preventing the transfer of the low order (to)accumulator bit to general storage.

TRANSFER T() ACUUULATGR (TA) (0010) (2) The K flip-hop and generalstorage remain unchanged. The low order bit of the accumulator is lost(reset to 0l). The number in general storage is transferred to theaccumulator, and replaces the number previously there (FIG- URE 3d).

The source of the number in this transfer is a general storage read head(38, 40), which, as has been previously noted, is six sectors removedfrom the general storage write heads. The actual path of transfer fromgeneral storage to the accumulator is L12-(G1, C109, G2,G3)-G4G7-F20-SF2 [FIGURE 6u), G60-G63- L1' [FIGURE 611]. G20-L7 [FIGURE6d). The F5 diodes in G3 and implicit in G1 through the A5 diode [FIGURE6p] and the L12 diode in G109 and G2 [FIG- 15 URE 6a] allow the path tooperate through G4 [F1G URE 6a].

As usual K and the general storage remain unchanged since no logic iswritten to change them. The F2 ipflop 54, which represents the generalstorage read llipflop in this command as is seen in FIGURE 3d, is resetoriginally as we enter the command. This means that is transferred intothe low order bit position of the acetirnulator at to, and consequentlythe low order bit previously there is lost (reset to 0).

lItlXTRACT-LEAI (lil/L) (0011) (3) If the K Hip-flop is 1 as thiscommand is entered, the extract order will be executed. lf K is 0" asthis Command is entered the leap order will be executed.

In the extract order, K and general storage remain unchanged. The loworder bit of the accumulator is lost (ire-set to 0). The number ingeneral storage is logically multiplied by the number in the accumulatorand the result is placed in the accumulator (FIGURE 3g).

K and the general storage remain unchanged for the usual reason that noaction is taken otherwise. In com puter logic terminology, a logicalmultiplication is simply an and gate. In other words, it takes a ls bitin both of the operands to yield a ls bit in the logical product for anygiven position of the number. The and gate in question is gate GSS(FIGURE 6:1). The path of the general storage operand up to this gate isL12-(Gl, 6109, G2, G3)G4-G7F20-SF2 [FIGURE 6u), G53- GSS [FIGURE 6:11,while the path of the operand from the accumulator is LS-LZ [FIGURE611], GS-GlZ-GIT- F30-SFI) [FIGURE 611], G55. The FS' diodes in G1, G3,and G8., and the L12 diode in G1109 and G2 allow these paths to operate.After the operands have merged in the and gate G55 to give the logicalproduct, the path continues as G55-G63-L1 [FIGURE 6u), G20-L7 [FIGURE6d] `As in the transfer to accumulator command, F2` once againrepresents the general storage read flip-flop and consequently is resetoriginally. Hence a 0 is transferred at to from F2 through` G53 to G55.With this input condition the output of G55 (representing the logicalproduct at to) must be 0, and consequently, the low order bit of theaccumulator is once again lost (reset to 0).

In the leap command, which is directed by the (00l l) code when 14:0, Kand general storage again remain un changed and the low order bit of theaccumulator is again reset to 0. However, the presence of this commandat 132 of F8 prevents the immediately `following 132, end-ofword clockbit from performing its normal changing of F8 (precess time) into F8(execute time). As a result, the accumulator word which normally wouldhave been processed by some instruction beginning with FS suddenly is`regarded by the computer as a regular instruction word and `isprecessed through the shift register to extract a new command. Thisreversal of roles between the current accumulator word and instructionword has the same eiect as if the drum had suddenly and discontinuouslylost or gained one revolution. This, therefore, immediately gives theinstruction portion of the A-I channel access to Words in the generalstorage track which it would otherwise have had to wait a full drumrevolution to achieve. Conversely, the accumulator portion of the A-Ichannel is given immediately access to words on the general storage drumfor which it would otherwise have had to wait the time of a full drumrevolution.

In order `to perform the foregoing task for the leap order an or gate G?(FIGURE 6p) is provided as an input to and gate G75 which is enabled att32. Gate G10? `is responsive to signals from the F3, F4, F5, and F6flip-flops which store the command that will be in the command registerat to. If this tetrad is F3', F4', F5, F6, and also if F1 `is set to "0(i.e. Fl), then a leap command exists and circuitry should be providedto inhibit the triggering of the F8 flip-flop. This is accomplished bymaking the operation of the "and" gute G75 16 contingent on the presenceof any one of. the de Morgan (primed) elements of the leap condition,Since the complement of an and expression is an or expression of thecomplemented individual terms, if either F1, F3, F-t, F5', or F6' ispresent at gate G107 at tgz, it means that the leap order is not presentand the normal generation of F 8 is permitted. Conversely, if none ofthe above five signals is present, a leap order is present, and gate Gis prevented from generating the auxiliary logical signal A14 (FIGURE16p) which is applied `to the ZFS termi nal of the F8 flipllop 68, asseen in FIGURE 6g.

OUTPUT (OUT) (0100) (4) If the busy signal (E10) is present, K is resetto 0 and the accumulator remains unchanged. If the busy signal is notpresent K is set to l, and the low order tetrad (four bits from t, tot4) of the accumulator is printed and cleared to Os. The remainder ofthe accumulator regenerates and the low order (to) bit of theaccumulator is cleared (reset to 0) regardless of the busy signal.

The first case to be analyzed in the output command will be where thebusy signal E10 is found to be present. As shown in the foregoing leapcommand, it is possible to examine an incoming code before it is fullyshifted into the command register, F4, F5, F6, F7, namely at tgz of F8when the command is arrayed in F3, F4, F5, F6.

In the case of the output command, we anticipate it at {32 of theprevious F8, and block the passage of the ls bit in the output operationcode (0100) from F4 to F5 if we find the busy signal present denoting anunsuccessful output. Thus if the output command is unsuccessful (E10present), it is automatically changed into a skip command as F8 changesto F8. Conversely, if F8' is reached and the output command is stillpresent, we know that it is a successful (E10 not present) output. TheG26 "or gate (FIGURE 6j) is the gate for transferring this l's bit, andthe path of the signal is E10'G26-G27-SF5. If E10 is present, obviouslythe path cannot operate and the F5 flip-flop 60 remains in the reset or0 state.

The normal path of information flow at this point in the command shiftregister is F4-G27-SF5. It will be observed that the G26 "or gaterepresents the only point where the busy signal, E10, enters the logic.Thus it may be said that the only function of the busy signal, ifpresent, is to convert the unsuccessful output command into a skipcommand. The denition and explanation of the skip command, as previouslydescribed, serves to complete the unsuccessful output.

If the busy signal is not found present and the output command arrivesintact in the command register at F8', the output is initiated. FIGURE4a represents the timing diagram for the output operation. In essence,the F2 and F3 flip-flops 54, 56 combine as a two stage tetrad counter asset out in Table 2, below.

The F2 F3 final condition extends across the rest of the word time, butat the end of t3, the output command code is reset to a skip command asshown by the state of the F5 ip-op 60 in FIGURE 4a. At the same time theK flip-flop F1 is set to a 1 in order to serve future notice that theoutput command was successful. Thus we observe that even with successfuloutput, the output cornmand only lasts four bit times before changing toa skip command.

Ordinarily, the F3 Hip-flop 56 serves as part of the accumulator loopwith the number word appearing at its output from t1 to x32. During theoutput command We wish to print out only the low order tetrad of theaccumulator, which ordinarily is available in the F3 flip-iiop 56 at t1to t4. For efficient minimization, however, we wish to use the F3 ip-oppart of the tetrad counter for output selection. Thus we tap theaccumulator loop one bit early at the L2 flip-flop 52, where the desiredinformation will appear at I.) to t3 rather than t1 to tt. Using thecombination of F2 and F3 to count to to r3 has already been described inconnection with Table 2 above.

After the output command changes into a skip cornrnand, thc flip-Hopresumes its normal role as part of the A41 rccirculating loop. Thus theremainder of the accumiuator is rccencrated and the low order terad isprinted and clear. However. one transition bit must be sct up correctlywhen the normal regeneration resumes. During the t to f3, the net L1[FIGURE 6N] will produce Os since no logic is written there whichresponds to 'the command refr'ster nal combination reprcscnting theoutput instruction. Then from t4 to fw the tunnel net will take theoutput of F3 because of the skip com d. From t5 to In, F3 trulyrepresents the remainder ofthe information from the accumulator (passinginto F3 from L2). At tit. however, F3 represents an inherited liif. fromthe last state. t3, of the tetrad count. Since it is indicated to cicarboth the low order tetrad and the ting bit, it is necessary for the netLt to produce G's from tanti. In order that the t4 bit be zcrocd, thetetrad count for I3 should include F3' rather than F3, and the tetradcounter therefore corresponds to the Gray or reflected binary codecount.

The four paths for the output information from L2 to the output deviceduring t@ to 13 are as shown in FlG- 'RE 6p as follows:LE-GtaS-Alt-GSTVEL LZ-GiSS-At- G84-vliz, LZ-G-Ai-GiriS-Ed, andvL2-G6S-ft4-Git5- Notice that the decoding for signals A28-A23 found onand gates GSE-G36 respectively, actually represent the countcombinations corresponding to the four bits [o i0 f3.

The path F-G'Y-Eln represents the fifth Wire in the five wire outputcode yielding thirty-two combinations. A more detailed description ofthis fifth Wire in the output code was previousiy described inconjunction with the primary fun-:tions of the F9 tiipdiop 7S.

in order to rcali7e the successful output command from the engineeringstandpoint. we need a common signal which will be activated whenc 'erany successful output occurs, r: .ss of thc tive wire output code. Thiscommon print" command signal is represented by the path Gdkilti, inFIGURE 6i.

The following logical paths are provided to enable the operation of theoutput counte Initially F2 and F3 must be react for the rst count, t0,of F3'. Since the reset is simply the nrime (De Morgan) of the set netfor both ot' these tina-Flops, we simply do not Write any logic in theset net operable at time tag of F8. At the end of tn however. the F3Hip-llop is set. The path for this is F2-G9AGi3-G17-F3SF3 [FIGURE obi.At the end of" t1 we must set F2. This is accomplished by the path (Gi.GIS?. G3)-Gfi-G'-l:2l--SF2 [FIG- URE. Gul. The F3 diode in Gi, and theF6 diodes in Gitti). G2. and G3 make this path possible. At the end oft;| We must reset F3. Once again this is achieved by writing no logic tocover the desired time (i2) in the set net, l: should be noted that F29and F39 represent the set nots for F2 and F3 dip-ilops respectively, andas previously stated. the structure of the logic is such that FZtl' andF33. represent the two reset nets respectively.

At the end of I2 the K (F1) lip-flop is set in order to later indicatethe successful output. This path is rcpresentcd by Gi-G4t7-SF1 [FIGURE6m). it was also necessary to reset Ft originally, at 132 of F3, in casethe busy signal was present to make the output command unsuccessful. Thepath taken for this is (E43-G49- 10 INPUT (is) (nun) (5) he itc-y do`V'n signal (Sib) is received, indicating a goo nput, i( is sct to l. rlcontents ot the keyboard are read into the f3. r1, t2, and t3 positionsot the accumui-.i if the keyboard character is a non-numeric charttiotone ol the digits through 9), a 1 is written e highes" order bitposition (32) ot the accumulator. s icmai der ot the accumulator iscleared to all D's. IC the keyboard (1o-.vn signal Sift is not received,K is reset to 0 and thc accumulator fills with either zeroes ormeaningless information (depending on whether ...f'ftches Si, S2, Sal,and are open or in the act ol bouncing or being set).

ty between the two operations is that Fl (the K p) is used to laterindicate whether or not the nica was succcsslul. FlGURE 4b shows atiming i .gram for both the successful and unsuccessful input. F11 isally reset as the input operation begins. This :shed at 132 of theprevious Fd by the path VFlGURE 6m] with the F3' diode making the pathpossible. At the end of t2, as Vl on the input timing diagram (FIGURE4b), high it the ltey down signal SiO is received a successful input.The path is SIO-G2-G43- [FIGURE om i. Il the ltey down signal is notrcceivL Fl remains reset. indicating that the input was umuccesstul. Thekey down signal (515)) as received trom the keyboard is nothing morethan a delayed common contact. In other words, when the lrcy down signalis received. wc are assured that the contacts providing the other inputsignals (S1, S2, S4, SS, and S11) have stoppebou ng and are thus sate tosample. Note that the contact for the lzey down signal Sit) itself maystill n: bouncing. but this docs not matter since the system .s it onlyat one discrete time interval, namely I2 dicated. ..ier requirement oithe input timing system is that trop set F3 if Fl has been set at thecnd of t2. i i be set at the end of t3. The path for this FE-G-J-GtG-Slf[FIGURE (dij. Observe that of f5. both F2 and F3 acted as the tctrad asthey did in the output operation. F2 and reset originally a: im ol FS.F3 was then of The paths necessary to achieve this f-ri'ricd in detailin the description of the tc ril counter ior the output operation. Thetctrad counter and its associated logic are substantially similar forboth the input and output operations.

the path of a bit from the keyboard to the write. head isSlWG'i'SGMGiGS/AIE [FiG. 6p|, G'SivGtES-Li' [,FIG. ont. Gld-L7 [FIG.6d]. The lat- 'irt o? this path. namely, AEE-GM-GtSS-LV-GZU-L7 unon Alorall tive of the information bits passing from the keyboard switchcontacts (Si, S2, S4, SS, and

ents the other four paths prior to t. merger at A12 in FIG. 6p. Duringf1, the path or" a 2 bit is SIZ-Gld-GIQLLAZ. At t2 the path of the 22bit is Saf-*Glhlh-Glti- Y2. The path of the 23 bit during r3 isSSAGTSGESA. Finally, the path ior uic nonmuznric (not 0 through 9)indicator bit at tgz is biiGlll4Git5-A12.

The following rep It should be noticed that normally, the low ordertctrad of the accumulator is applied from i( to l( to the write head.The successful input operation, however records the low order tetrad inthe accumulator in the t0 lo t3 bit positions, cle-.trs the accumulator(to s) from r11-tgl, and, il necessary, inserts the non-numeric tetradindicator bit at tag. The clearing of the accumulator from t4 to rs1 isaccomplished by simply writing no logic in the net (Ll) to do otherwise.

A successful input command is usually followed by a shift left command,explained in greater detail below. This shifts the high order in bit(representing the nonnumeric tetrad indicator bit) into the K llip-ilopwhere the programmer can then test for its presence. The shift leftcommand will also shift the low order tetrad from (t0 to t3), to (t1 tot4), and thus place it in its normal position in the accumulator.

The input operation normally serves as the lirst of a group of fouroperations. The second operation of the group will be a jumpconditional, explained below, which tests Whether or not the input wassuccessful by checking the K Hip-flop. A shift left command (as beforenoted) then follows the jump conditional provided the input wassuccessful. The fourth operation of this group will be another jumpconditional which will test for the pres- -t ence of the non-numerictetrad indicator bit by means of the K flip-Hop.

SUBTRAC'I (SUB) (0110) (Il) K is reset to G initially. age is subtractedfrom the number in the accumulator, and the result replaces the numberin the accumulator. If the general storage number is larger than thenumber originally in the accumulator, K is set to a 1. The number ingeneral storage remains unchanged. The low order (to) bit of theaccumulator is cleared (reset to 0). (FIGURE 3h).

The L5 gate circuit represents the sum-difference net for theadder-subtractor unit. The path of the resultant signal from L5 to theA-I write head is LS-GSS-G-Ll' [FIGURE 611], G20-L7 (FIGURE 6d].

It may be noted that in binary addition or subtraction, the surn anddifference digits are identical but that the borrow and carry differ.

This is more easily noted from Table 3A below, in

Which F1 represents the carry-borrow, F2 represents the A major purposeof the K (F1) llip-ilop in our invention is to serve as the carry-borrowflip-flop for the adder subtractor unit. Consequently, at the end of anF8 executing an addition or subtraction operation, F1 will be left high(set to l) if wc have had an overflow in the addition or if we havesubtracted a larger number from a smaller one. It should be observedthat in general F1 does not change during an F8 word time, so that inessence it carries forward information from one F8' to the next F8. Thusif we followed a subtraction operation with a jump conditional(conditional on K1 to be explained below) we could branch the programdepending on whether or not subtraction resulted in a change of sign.

The number in general storlll) As can bc seen from Table 3A above, thethree inputs to the addcr-subtractor unit of FiG. 6e are F1, F2, and F3.As previously stated, F1 represents the carry-borrow ilip-llop. F2represents the operand from general storage in the addition andsubtraction operation, and its path from general storage to F2 isLIZ-(Gl, G1G9, G2, GB)HG4G7"-FZO-SF2 (FIG. (im. The F6 diode in G1, theL12 diode in Gl@ and G2, and the F4 diode in G3 allow this path tooperate. Similarly, F3 represents the operand from the accumulator whichis the augend and minuend in the addition and subtraction operations.The path of this operand from the A-I read head to F3 is LSLZ (FIG.611], GS-GIZ-Gl-FSQLSFT (FIG. 611], with the FS diode in G8 allowing thepath to operate.

The combining of the three inputs (Fl, F2, and F3) to form the sum (orthe difference) in the addition and subtraction operations isrepresented by the common mixing paths (FZ-AillvF-(G'g-AZ, GSH-Ail, G81-AZZ, G32-A23) (FIG. (1p1, (Gli, G22., G23, G24)- GZS-LS (FIG. 66], thethird input Fl enters into the nixing path through gates GDL-G25 asfollows: F1- G1-G22, G23, GIM-G2545. The purpose of this mixing path inthe adder-subtractor is simply to give a sum (or difference) on the L5output line whenever any one or all three of the inputs (FI, FZ, and F3)are present. Thus, the sum-difference logic for L5 may be Written as setforth in Table 3B. This logical statement L5=1 can be expressed in theconventional terminology in which iand" groups are connected by dots andin which of the sum-difcrence gate at t0 is condition is Fl.F2'.F3'.Thus the low order bit of the accumulator is reset (cleared to 0) inboth thc addition and subtraction operations. F2 and F3 are low at tusimply because no logic was written to set them at x32 ot` the previousF8. The carry-borrow flip-flop F1 was reset to 0 at the end of F32 ofthe previous FS by means of the path G48-G49-G52-ZF1 (FIG. 6m] with theF3' diode allowing the path to opcrate.

It is pertinent to note that up until this point a cornmon description(with the corresponding logic and gating paths) has served for both theaddition and subtraction operation. The only difference between the twooperations is the logic for setting and resetting the carryborrowiiip-op F1 (K) during F8'. It has already been observed that F1 is resetinitially in both operations.

With reference to FIG. 6m, in subtraction, the path for setting F1 highas a borrow corresponding to Table 3B above is (F2, F3)-G82-A23 (FIG.6Fl, G44G47 SFI (FIG. 6111]. The corresponding reset path for F1 insubtraction is (FZ, F3)-Gl}-A2I (FIG. 63], G5l- The initial output 0because the input GSZ-ZFl (FIG. 6rn]. In thc addition operation the pathfor setting F1 high as a carry is (FZ, F3)-Gtl-A22` (FIG. 611],G42.-G43-G4i-SF1 IFIG. 6m], with the F6 diode in Gl?. allowing the pathto operate. The corresponding reset path for F1 in addition is (FZ',F3'l-G79- All) (FIG. Gpl, G58-G52ZFI (FIG. 6111].

ADD (Aint) (m11) (7) K is reset to 0 initially. The number in generalstorage is added to the number in the accumulator, and the resultreplaces the number in the accumulator. If the result in the accumulatoroverflows (exceeds thirty-two bits) K is set to a l. The number ingeneral storage remains unchanged. The low order bit 0f l HCCUmUllO 1Scleared (reset to 0).

A complete description of the ad dition OPCTHOH Wim the correspondinglogic and gating Pftlls WHS COVcrCd 21 under the previous description c.the substraction operation. As previously mentioned. a commondescription serves both oi these operations aside from the logic oiC thecarry-borrow flip-dop F1 (K) which was fully set forth above.

JUMP (J) (1000) (8) K. general storage. and accumulator remainunchanged. A new instruction word for general storage is brought intothe instruction portion of the A-I channel during the next word time.The first (high order) tetrad of this new instruction word is executedthree word times later (or equivalently four word times after the jumpcommand was initially executed).

The jump command represents the first of tour (jump, change track, jumpcondition, and jump delay) displacement addressing instructions. Theyare control instructions (in contrast to arithmetic instructions such asaddition) in that they operate on the instruction portion rather thanthe accumulator portion of the A-l channel. The normal routine ofsetting up (precessing in) a new command during and then executing itduring the next word time F3 can only be applied to the arithmetic typeinstructions and the skip command. This results from the fact that onlythe accumulator is available during Fti'. The control type instructionsare set up during F8 as usual, but we find it impossible to execute themthe next succeeding F3 word time, since the instruction portion of thechannel is simply not available during F8.

The purpose of the jump command is to transfer a new instruction wordfrom general storage into the A-I channel. Supposedly we have alreadyexecuted all of the eight commands found in the previous instructionword, and now must bring in a new instruction word in order to keep thecomputer sequencing. Ordinarily we would have to program the jump as thelast (eighth or low order tetrad) command in the old instruction word inorder to bring in a new instruction word. Thus every instruction Wordwould only have seven useful commands, with the eighth command beingused as a jump in order to replace the instruction word with a new orteAln our invention, however. all eight commands in the instruction wordare useful. The jump command need never be programmed as the eighthcommand in order to transfer in a new instruction word. The reason forthis is the automatic jump feature.

To the computer the automatic jump looks exactly as if a jump commandhad been programmed as a fietitious ninth command on the low order endof the instruction word. Though the automatic jump need not heprogrammed, the regular time ailotted for the execution of a jumpcommand must also he allowed for the automatic jump when writing aprogram. ln other words, the programmer knows that the computer is goingto introduce a ninth command, namely, the automatic jump, after all theinstructions of a word have been executed. Thus we see that thiscomputer has automatic sequential control for instruction words.

Though it is not programmed, the realization of the automatic jumpfeature in the computer is as follows:

When the new instruction word is transferred from general storage to theAHI channel (as a result of a jump type command), it occupies theposition (L32 in the orders channel. During this transfer, however, a lsbit is always deposited into the low order (iiag) t0 position of theinstruction portion of the A-l channel. The l`s bit will precess up theloop with the instruction word. It is this l`s bit that ultimately isexecuted as the automatic jump command.

At this point it is pertinent to observe some properties ot theinstruction word precesslon in the A-I channel. This is a high order orlong type precession in that the circulating information is displaced toa position four hits later in the word time after each prccession. Thusthe tetrad of information representing the eighth command in theinstruction word will move from i114 to 15gg after the initialprcecssion.

This preccssion is achieved during F8 by passing the A-I channel readoutput through the command shift register (four bit delay) and back tothe A-Iw write head. This is represented by FIG. 3b and the path L8 SLElllG. 61:1, (G19.y GlU-AGM-GW-F-SFS lFiG. 6bl,(GS4-G64-SF4)(G65G66-'7F4) IFIG. 60], (G26- G27-SFS)(G2E-G2`=-ZF5) |FEG.6i). (G36-SF6) (G37-G3-ZF6) lFlG. dit. (G3t'!SF7)(G3'i-G5ZE7) (PEG. 6U,G62-G63-Lll' [FIG 611], G-Z-L? IFlG. 6d?. The F2' diode in G10, and thetpgz' diode in Gll. and the Al diodes in G65, G27, G25, G35, G37, G30.G34, and G62 make this path possible. The F4 diode in gate G64 isredundant logically, but is necessary for signal loading considerations.The A1 signal in this path represents the "advance" signal for thccommand shift register (F4-F7). The logic for this advance signal isrepresented by the path G93-G94-A1 (FIG. 6121.

The path for the insertion of the l`s bit (representing the automaticjump) into the orders channel to t (when the instruction Word is beingtransferred from general storage to the order channel) is G74-A13 (FIG.Gpl, Gl5-Gl7-F3-SF3 (FIG. 6M, G81-A22 (FIG. 611], G56-G63-L1' IfFIG.Gull, G20-L7 (FIG. 6d'l. Note that while the ls bit is originallyinserted (G15) at 132 of the previous F8', it picks up a unit delay ingoing through the F3 flipdlop so that it appears at the A-Iw write head(L7) at to of the following F8.

After each precess time circulation, the high order terad of the orderschannel (which occupied the position rggg) is left in the command shiftregister, while the second highest order tetrad (tggga) is precessed upinto the hielt order tetrad position. This tetrad which pre cesses oitthe high order end of the A-l channel and left in the command shiftregister is the command that will be executed the next F3 word time.

During the precession, however, four new bits must have shifted into thelow orde" end of the orders channel during m3 to displace the inirmation toward the higher order end. As indicated by the logical gatingpath, we see that F7 is the path source for these bits. Thus we observethat ordinarily the old command code (which was just decoced from thecommand shilt register and executed during the F3 word time previous tothe precession) would be the source of the tour additional bits inquestion. Allowing this situation to occur would continually recirculatethe instruction word and require that a jump instruction he included inevery instruction word. Therefore, the A?. function net (whichrepresents the common reset signal for the command shift register)resets the commend shift register to all G`s at the ends of tgt; or"every Fti'. This is achieved in the A2 net by the path AES-G92A2 snownin FIG. 6p. The four paths from A?. to the command shift register areAZ-G66-ZF4 (FIG. 60j, iXi-Gin UWG. tijl, AZ-GSS-ZF (FIG. (til. and.it2-Ga`lf-G3,3G35Z `7 (FIG. 61'1. In the last ot the four paths, G3iinhibits the resetting of F7 during the change track and jump delaycommands. The reason for this will be covered later during thedescription ot' these commands.

Thus wc observe that as a result of the A2 signal at tgz of the previousFS', four 0`s are shifted into the A-I channel at the low order end,umg, during every F8. Thus as the precessions of the instruction wordcontinue, the instruction word eventually fills up with (Vs from the loworder end. Another way of looking at this is that for every command(four bits) processed ott the high order end oi the instruction wordinto the command shift register, there is an equivalent four bits (allO's) shifted into the low order end of the word.

New let us return to the is bit that was placed in the A-I channel atthe low order end t0 when the new instruction was transferred in fromgeneral storage.

1. IN A DIGITAL COMPUTER, THE COMBINATION COMPRISING: A REGISTER FORSTORING BIVALUED SIGNALS ARRANGED IN A PLURALITY OF ALTERNATE GROUPS,THE FIRST GROUP OF SAID PLURALITY REPRESENTING AN ACCUMULATOR NUMBER ANDTHE SECOND GROUP OF SAID PLURALITY REPRESENTING INSTRUCTIONS, SAIDSECOND GROUP BEING FURTHER ARRANGED IN A PLURALITY OF SUB GROUPS OFSIGNALS, AT LEAST ONE SUB GROUP OF SAID LAST NAMED PLURALITYREPRESENTING AN INSTRUCTION CORRESPONDING TO AN OPERATION TO BEPERFORMED UPON INFORMATION IN SAID COMPUTER; MEANS FOR CIRCULATING ANDSERIALLY PRESENTING SIGNALS STORED IN SAID REGISTER; OPERATING MEANSCONNECTED TO SAID CIRCULATING MEANS AND OPERABLE IN RESPONSE TO A FIRSTSUB GROUP OF SIGNALS REPRESENTING AN INSTRUCTION TO PERFORM ACORRESPONDING OPERATION UPON INFORMATION IN SAID COMPUTER AND, IN EACHSUBSEQUENT CYCLE OF OPERATION, BEING OPERABLE IN RESPONSE TO ANOTHERSIGNAL OF SAID SUB GROUPS FOR PERFORMING AN OPERATION CORRESPONDINGTHERETO, EACH CYCLE REQUIRING ONLY THE TIME NECESSARY FOR READING THESIGNALS OF ONE EACH OF SAID FIRST AND SECOND GROUPS.